In the fabrication of semiconductor devices, it is often necessary to make electrical interconnections at selected locations between two vertically separated metal layers. One technique for making such electrical interconnections is known as the "via" process. The via process simply etches a hole through an insulator which resides between the two separated layers. When the top one of the two metal layers is deposited, it contacts the bottom layer through the hole.
Alternatively, such electrical interconnections may be provided by the use of pillars. Pillars are conductive, vertically extending posts which are formed on the bottom of the two vertically separated layers and which extend to the top layer. Pillars may be formed by an additive process in which the pillars are added to the bottom conductive layer at desired locations. Alternatively, pillars may be formed by a subtractive process in which both a pillar and the bottom conductive layer are formed from a thick conductive sheet. This conductive sheet may contain a plurality of individual conductive layers.
One particular subtractive process for the formation of pillars is disclosed in U.S. patent application Ser. No. 123,754, filed Nov. 23, 1987, assigned to the assignee of the present invention, and incorporated herein by reference. In this process both a pillar and a pattern defined in the bottom one of the two vertically separated metal layers are individually aligned with a common feature, such as a contact. Consequently, the pillar and the pattern vertically align with one another. However, this alignment process causes a manufacturability problem.
Specifically, the first alignment step vertically aligns a pillar pattern with the common feature. Due to practical implications of semiconductor fabrication, the pillar pattern may not precisely align with the common feature but will reside within a predetermined lateral distance of the common feature. This distance represents a tolerance which is defined by photolithographic and other manufacturing limits. For example, if this tolerance is .+-.1/2 micron, as a worst case situation the pillar may be laterally skewed up to 1/2 micron away from the common feature.
The second alignment step aligns a lead pattern formed in the bottom conductive layer with the common feature. Again, the lead pattern may be laterally skewed away from vertical alignment with the common feature by a worst case distance established by the manufacturing tolerance. When these two alignment steps combine the manufacturing tolerance doubles. For example, a pillar pattern may be laterally skewed away from the common feature to the right by 1/2 micron, while the lead pattern is laterally skewed away from the common feature to the left by 1/2 micron. With the 1/2 micron tolerances, the pillar and the lead pattern may be skewed one micron away from each other.
One solution to the doubled tolerance problem is to dimension the pillars and leads to compensate for this worst case double-skewing effect. For the above example, this compensation is equivalent to utilizing .+-.1 micron layout rules even though a fabrication processes otherwise successfully produces semiconductor devices using .+-.1/2 micron layout rules. However, such a solution undesirably decreases the density of the semiconductor device being fabricated.
Accordingly, a need exits for a process that forms pillars without subjecting the layout to the above-mentioned doubled tolerance effect.